AMD Ryzen ThreadRipper PRO 7975WX / 4 GHz processor - PIB/WOF

SKU 100-100000453WOF
Product Description:AMD Ryzen ThreadRipper PRO 7975WX / 4 GHz processor - PIB/WOF
Product Type:Processor
Processor Type:AMD Ryzen ThreadRipper PRO 7975WX
Number of Cores:32-core / 64 threads
Cache:128 MB
Compatible Processor Socket:Socket sTR5
Processor Qty:1
In Stock(4)
  • Specifications
  • Description
General
Product Type:Processor
Processor
Type / Form Factor:AMD Ryzen ThreadRipper PRO 7975WX
Number of Cores:32-core
Number of Threads:64 threads
Cache:128 MB
Cache Memory Details:L1 - 2 MB ¦ L2 - 32 MB ¦ L3 - 128 MB
Processor Qty:1
Clock Speed:4 GHz
Max Turbo Speed:5.3 GHz
Compatible Processor Socket:Socket sTR5
Manufacturing Process:5 nm
Thermal Design Power:350 W
Thermal Specification:95 °C
PCI Express Revision:5.0
PCI Express Lanes Qty:148
Architecture Features:AMD EXPO Technology, AMD RyzenTechnologies, "Zen 4" Core Architecture, AMD Precision Boost 2 Technology, AMD PRO technologies
Miscellaneous
Package Type:AMD Processor in a Box without heatsink/fan (WOF)
vis mere
AMD Ryzen Threadripper PRO processor is the first and only professional workstation-caliber CPU to exploit a 7 nm silicon manufacturing process, allowing engineers to double the density and fueling the transistor budget needed to substantially drive-up core throughput. With the unveiling of the first generation of "Zen" CPU technology, AMD disrupted the status quo with a microarchitecture completely rebuilt from the ground up and optimized for modern single and multi-threaded workloads. With the Threadripper PRO processor's "Zen 2" microarchitecture, improvements are many, but two carry most of the weight, especially where high demand professional computing is concerned: up to 15% faster instructions per cycle (IPC), and an impressive quadrupling of the peak floating point throughput rate. The former comes primarily by the way of improved branch prediction and pre-fetching, supported by much deeper and broader allocation of cache, while the latter is the result achieved by both doubling the width of the FPU data path and doubling density. Supporting the increased compute throughput, architects doubled load-store bandwidth and dialed up dispatch and retire bandwidth to minimize the chances the higher throughput ALUs would be starved of data.




The technical details come from 3rd party. edgemo is not responsible for any errors.

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